Abstract
ATLAS is one of the four major experiments at the Large Hadron Collider at CERN. The tracking performance of the ATLAS detector relies critically on its 4-layer Pixel detector, located at the core the ATLAS tracker. During operation at instantaneous luminosities of up to 2.1 × 1034 cm−2 s−1 the frontend chips of the ATLAS innermost pixel layer experienced single event upsets affecting their global registers as well as the settings for the individual pixels, causing, amongst other things, loss of occupancy, noisy pixels, and silent pixels. A quantitative analysis of the single event upsets as well as the operational issues and mitigation techniques are presented.
Highlights
Single Event Upsets in the ATLAS IBL Frontend ASICs at the Large Hadron Collider at CERN
The pixel local configuration consists of 13 bits in each pixel: Enable, TDAC, Injection Caps choice (2 bits), HitBus, FDAC
SEUs in the global and local pixel configuration memories were observed during LHC fills and have several consequences: steps in low voltage consumptions, module desynchronization, dead modules, quiet pixels, broken clusters, noisy pixels etc
Summary
The pixel local configuration consists of 13 bits in each pixel: Enable, TDAC (thresholds 5 bits), Injection Caps choice (2 bits), HitBus, FDAC (feedback current 4 bits). In this case 0 → 1 flips in pixel memory are much more frequent than 1 → 0 flips. The average rate of the SEU/SET bit flips in pixel memory was studied as a function of the bit number (0-12).
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