Single-event-upset sensitivity analysis on low-swing drivers.

Nor Muzlifah Mahyuddin,Gordon Russell

doi:10.1155/2014/876435

Nor Muzlifah Mahyuddin, Gordon Russell

Open Access

https://doi.org/10.1155/2014/876435

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Abstract

Technology scaling relies on reduced nodal capacitances and lower voltages in order to improve performance and power consumption, resulting in significant increase in layout density, thus making these submicron technologies more susceptible to soft errors. Previous analysis indicates a significant improvement in SEU tolerance of the driver when the bias current is injected into the circuit but results in increase of power dissipation. Subsequently, other alternatives are considered. The impact of transistor sizes and temperature on SEU tolerance is tested. Results indicate no significant changes in Q crit when the effective transistor length is increased by 10%, but there is an improvement when high temperature and high bias currents are applied. However, this is due to other process parameters that are temperature dependent, which contribute to the sharp increase in Q crit. It is found that, with temperature, there is no clear factor that can justify the direct impact of temperature on the SEU tolerance. Thus, in order to improve the SEU tolerance, high bias currents are still considered to be the most effective method in improving the SEU sensitivity. However, good trade-off is required for the low-swing driver in order to meet the reliability target with minimal power overhead.

Highlights

In today’s deep submicron, technology scaling relies on reduced nodal capacitances and lower voltages in order to improve performance and power consumption
In terms of SEU tolerance, previous results indicate that, by introducing a high bias current into the design which will improve the reliability towards SEUs, the power consumption is significantly increased
One method of increasing W/L ratio or choosing larger effective transistor length shows that the improvement is less significant than employing high bias current

Summary

Introduction

In today’s deep submicron, technology scaling relies on reduced nodal capacitances and lower voltages in order to improve performance and power consumption This includes shrinking the active chip area and increasing the layout density. This will reduce the critical charge required to upset a circuit node, making these submicron technologies more susceptible to soft errors. Since radiation-induced faults such as an SEU have received significant attention in recent years, especially in deep submicron regime, it is important to investigate the performance of the low-swing driver against SEU effect using circuit design approach. Several additional approaches to improve the SEU tolerance will be addressed, by incorporating the key parameters identified beforehand

SEU: Background Review

Measurement and Modeling of an SEU

Results and Discussion

Conclusions