Single Electron Tunneling based computation

Abstract

The expectation that current semiconductor technologies (CMOS) cannot be pushed beyond certain limits especially with regard to power consumption and scalability, has motivated intensive research into a wide variety of alternatives. Single Electron Tunneling (SET) technology has attracted interest in this context due to its potential for extremely low power consumption. Based on the tunneling of electrons through junctions, SET differs fundamentally from CMOS, and opens up avenues for new computational paradigms. In the last few years there has been considerable interest in researching methods to effectively utilize the basic SET properties. This paper presents an analysis of various design styles that might be potentially utilized in conjunction with SET devices. We discuss and compare four SET designs styles as follows: CMOS-alike logic, based on SET transistors; Single Electron Encoded Logic, based on threshold gates that utilize the intrinsic behavior of SET tunnel junctions; Electron Counting, based on direct encoding of integers as charge combined with computation via charge transport; and Brownian Delay Insensitive Circuits, which are robust to signal delays and utilize signal fluctuation in the computation process. Our analysis clearly indicate that the approaches that make a better use of the specific properties and behavior of the SET devices can potentially provide better performance in terms of delay and energy consumption at a lower area cost.