Abstract
It is generally accepted that fundamental physical limitations will eventually inhibit further (C)MOS feature size reduction. Several emerging nano-electronic technologies with greater scaling potential, such as single electron tunneling (SET), are currently under investigation. Each of these exhibit their own switching behavior, resulting in new paradigms for logic design and computation. This paper presents a case study on SET based logic. We analyze and compare three different SET designs styles as follows. First, SET transistor based designs that mimic conventional CMOS. Second, single electron threshold logic based on the voltage threshold of SET tunnel junctions. Third, electron counting logic based on direct encoding of integers as charge combined with computation via charge transport.
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