Simultaneous Routing, Buffering, and Power Planning in Floorplan Design

Abstract

With the advances of VLSI technology, deep-sub-micron (DSM) fabrication process becomes more and more popular. In a DSM design, the congestion dominated by interconnections has become an important design issue. Some other previously overlooked effects, such as IR-drop and ground-bounce are also becoming the first-order design parameters to consider. Both the interconnection and power delivery effects are difficult to predict precisely during early design stage. Therefore, the VLSI physical design flow for DSM fabrication technology is typically performed in an iterative and incremental style. This research attempts to decrease the design iterations in such an iterative design flow by excluding the factors that are inclined to cause design failure. We propose two main problem-solving mechanisms at the foorplanning stage: interconnection evaluation and power delivery evaluation. The former takes congestion into account, the latter focuses on IR-drop and ground bounce. These two problems are independent for most design cases, but are related for some design cases. Therefore, different strategies have to be proposed for different conditions. For the problem of power delivery evaluation, a Successive Elimination (SE) power planning algorithm is proposed to evaluate IR-drop’s of power inputs. In comparison to the existing approaches, SE algorithm features simple data structure and thus a significantly efficient evaluation speed. For the problem of interconnection evaluation, we proposed a Manhattan Routing (MR) algorithm and a Maze-based between-buffer Routing (MBR) algorithm, which apply the existing Independent Feasible Region (IFR) technique to decide buffer locations and are responsible for the simultaneous routing and buffering, respectively in a Manhattan-type and a detour-type of interconnections. The MR and MBR algorithms are then respectively revised as a Fast Manhattan Routing (FMR) algorithm and a Detour Routing (DR) algorithm. The FMR and DR algorithms adopt the technique of Buffer Sit Approach (BSA) instead of IFR to decide buffer locations. In comparison to the MR and MBR algorithms, the FMR and DR algorithms feature a more efficient congestion evaluation. Moreover, as we have observed that BSA may insert buffers to congested regions on a dominant bus, an extended version of BSA, enhanced buffer site approach (EBSA), is proposed, which can evenly insert buffers to a dominant bus. For a low cost design or a design with limited layers, where power lines and signal nets are inevitably put on the same layer(s), the integration of interconnection evaluation and IR-drop/ground-bounce evaluation facilitates a more precise prediction Thus, a procedure is proposed to integrate power delivery planning, routing, and buffering in an iterative floorplanner such that IR-drop, ground-bounce and different kinds of congestions in a design can be simultaneously evaluated. To support more precise evaluation and to facilitate the interactions between power delivery planning and congestion evaluation, the SE algorithm is further enhanced as an Ordered Successive Elimination (OSE) algorithm to handle ground bounce additionally and to generate information of power lines. Also, a Fast Power line and Signal net Manhattan Routing (FPSMR) algorithm is included in our procedure to perform congestion evaluation of power lines and signal nets. The FPSMR algorithm is analogous to the FMR algorithm. The only difference is that, before operating as the FMR algorithm doing to evaluate congestion, the FPSMR algorithm has to invoke a Power line Manhattan Routing (PMR) algorithm to route power lines generated by the OSE algorithm. Sharing an agile grid data structure, the algorithms and procedures presented in this Dissertation feature consuming less memory as well as providing a quick and effective evaluation. An effective evaluation facilitates filtering out designs with worse routability or inferior performance. Besides, as these evaluations are performed at an earlier design stage, the design iteration is thus effectively decreased. Since the evaluation speed of these algorithms and procedures is very fast, the operation speed of an iterative floorplanner integrating the proposed procedures can be much improved.