Simultaneous Optimization of Standby and Active Energy for Sub-Threshold Circuits

Ali T Shaheen,Saleem M R Taha

doi:10.5121/vlsic.2016.7601

Abstract

Increased downscaling of CMOS circuits with respect to feature size and threshold voltage has a result of dramatically increasing in leakage current. So, leakage power reduction is an important design issue for active and standby modes as long as the technology scaling increased. In this paper, a simultaneous active and standby energy optimization methodology is proposed for 22 nm sub-threshold CMOS circuits. In the first phase, we investigate the dual threshold voltage design for active energy per cycle minimization. A slack based genetic algorithm is proposed to find the optimal reverse body bias assignment to set of noncritical paths gates to ensure low active energy per cycle with the maximum allowable frequency at the optimal supply voltage. The second phase, determine the optimal reverse body bias that can be applied to all gates for standby power optimization at the optimal supply voltage determined from the first phase. Therefore, there exist two sets of gates and two reverse body bias values for each set. The reverse body bias is switched between these two values in response to the mode of operation. Experimental results are obtained for some ISCAS-85 benchmark circuits such as 74L85, 74283, ALU74181, and 16 bit RCA. The optimized circuits show significant energy saving ranged (from 14.5% to 42.28%) and standby power saving ranged (from 62.8% to 67%).

Highlights

Modern digital CMOS circuits explore dramatically leakage power increasing with each generation
The well-known CMOS sub-threshold circuits are considered candidate solution for energy constrained-low speed applications since it can significantly reduce energy per cycle (EPC) due to its very low supply voltage. These circuits suffer from the large delay which increases exponentially due to the exponential relation between the sub-threshold current and the supply voltage whereas the delay in above threshold operation increases according to αpower law [1]
We propose a simultaneous active and standby modes energy optimization technique for 22nm sub-threshold circuits with non-zero standby applications

Summary

Introduction

Modern digital CMOS circuits explore dramatically leakage power increasing with each generation. The well-known CMOS sub-threshold circuits are considered candidate solution for energy constrained-low speed applications since it can significantly reduce energy per cycle (EPC) due to its very low supply voltage. These circuits suffer from the large delay which increases exponentially due to the exponential relation between the sub-threshold current and the supply voltage whereas the delay in above threshold operation increases according to αpower law [1]. The sub-threshold operation is a weak inversion mode depends on the sub-threshold current as the main source of current This current is summarized in Equation (1)

Methods

Results

Conclusion