Performance of submicron CMOS device and logic gates with substrate biasing

Abstract

Body bias engineering was investigated in the viewpoints of both device and circuit performance. For reverse body bias to suppress standby power, it was found that there might exist an optimal reverse body bias for minimizing the off- state leakage current. The optimal reverse bias value was found to decrease as the temperature goes down and varies form process to process, and technology generation. It is also found that the reduction in leakage current with reverse body bias is enhanced as the device temperature goes up and diminished as the temperature goes down. For forward body bias to improve the performance, it is found that a forward body bias can suppress short channel effects and improves Vt roll-off. Simulations on performance of typical CMOS logic gates shoed that forward body bias can reduce the gate delay and the improvement is enhanced as the power supply deceases. Power and power delay product will not be improved if forward body bias is applied on the entire circuit. A good strategy is to apply a forward body bias on critical path only to improve speed with minimum power trade-off.