Simultaneous Multi Voltage Aware Timing Analysis Methodology for SOC using Machine Learning

Abstract

To improve gross margins, the semiconductor industry is focused on the PPA (power, performance, area) matrix of the SOC. The current trend is to put more IPs on the chips to enable multiple functionalities to support various applications. To optimize PPA of such SOCs, multi voltage and multi power domain design techniques are used due to which the timing signoff of the chip has to be done on multiple corners and multiple modes (MCMM). Single voltage timing analysis is easier. With the multi-level supply voltage and dynamic scaling features, the timing analysis complexity increases because timing signoff has to be done on different voltages and cross-voltage paths. Multi-voltage designs need exhaustive analysis of cross voltage domain paths to make sure all worst-case paths are identified under all voltage combinations. With numerous operating PVT corners, timing analysis across corners is very challenging. Simultaneous multi-voltage aware analysis (SMVA) do the analysis of all cross-domain paths under all voltage scenarios in a single run, without the need for margining that can add pessimism. In this paper, we propose a machine learning model, based on bigrams of path stages, to predict the timing slack divergence and cell delays across voltages. We identified the circuit parameters which affects the cell delays due to voltage changes and thereby causing the differences in the endpoint arrival times. We use the timing analysis data of a given testcase at multiple voltages and with the use of Classification and regression tree (CART) approach we develop a predictive model for the new arrival times due to the change in voltages. Experimental results show that our model is able to predict the timing path slack divergence with ~97% accuracy at different voltages on both clock and data paths with a lower turnaround time including the cross-voltage timing paths.