Multi-corner multi-voltage domain clock mesh design

Abstract

This paper introduces a novel multi-voltage domain clock mesh design methodology that is effective under multiple process corners. In multi-voltage designs, a single clock mesh that spans multiple voltage domains is infeasible due to the incompatibility of voltage levels of the clock drivers on the electrically-shorted mesh-each voltage domain requires a separate mesh. The skew among these isolated meshes need to be matched and a novel premesh tree synthesis is required to tolerate the impact of PVT variations exacerbated due to the separation of clock meshes for multiple voltage levels. The experiments performed with the largest three ISCAS'89 benchmark circuits operating at 500 MHz, 90 nm technology and 3 process corners show that: 1) The multi-voltage domain clock mesh can achieve up to 42% lower power on average with 39.04 ps skew, as low as ≈1.95% of the clock period, on average over a typical single voltage domain clock mesh, and 2) multi-corner optimized multi-voltage domain clock mesh can decrease the global skew of all corners by 190.42 ps on average over a multi-voltage domain clock mesh optimized for a single corner with a 15% degradation in power consumption necessary for variation-tolerance.