Abstract
Actuality of investigation. Nowadays the leading developers of microelectronic devices continue the elaboration of completely custom-made key microelectronic systems modules, such as microprocessors cores, microcontrollers in a mode where the final composition of library elements is not known beforehand, and the design is performaning at the extremely low transistor level. However, automation of logic and layout synthesis process for a completely custom design is difficult due to significant increase of problem complexity with increasing integration of microelectronic systems and decreasing technology sizes to 22nm and below. The purpose of this paper investigation is FinFET layout generation methods for synthesis of elements with regular layout structure in polysilicon and diffusion layers for the full custom data flow.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
