Abstract
This paper describes simulation results for the collector resistance of a vertical pnp for complementary bipolar LSI, which can be fabricated by adding a p-well formation to the npn process[1]. It is found that the performance f T and current driving capability of such pnp devices are limited by the collector resistance R c. A simple method for extracting the lumped R c from a device simulator is described. The simulations show that the collector charging time adds a significant amount to emitter-to-collector delay, and the quasi-saturation in the collector junction limits its current driving capability. These observations highlight the importance of collector design in high performance pnp.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.