Simulation study on single-event burnout reliability of 4H-SiC trench gate MOSFET with combined P-buried layer

Abstract

In this article, the purpose of this numerical study is to investigate the rated 3.3-kV SiC power gate trench MOSFET structure with ground and float p-buried layer (DGF-MOS). The simulation results show the introduction of ground and float p-buried layer and upper drift layer optimized breakdown voltage (BV) the specific on-resistance (Ron,sp), and gate drain charge (Qgd,sp), thus the figure of merit (BV2/Ron,sp) is improved by 130 % and the figure of merit (Ron,sp × Qgd,sp) is reduced 173 % compared with the conventional SiC power gate trench MOSFET (CT-MOS). Additionally, the single-event burnout (SEB) simulation results show that the critical degradation threshold of CT-MOS structure is 900 V at LET = 0.5 pC/μm. The robustness of the DGF-MOS structure design to heavy ions was simulated. The results show that the maximum temperature peaks around the gate trench and substrate junction of the DGF-MOS structure could both be effectively suppressed due to the decrease in electric field peak. Consequently, the DGF-MOS structure showed a severe denaturation threshold of 1500 V, which was 66.6 % higher than that of the CT-MOS structure.