Simulation of a Short-Channel 4H-SiC UMOSFET with Buried p Epilayer for Low Oxide Electric Field and Switching Loss

Abstract

A 4H-SiC UMOSFET structure, which can significantly reduce both the electric field in the gate dielectric and the total switching loss, is characterized by simulation in this letter. The presented structure features a buried p layer (BPL) inside the drift region and an n implanted region N implant under the trench bottom. Based on the epitaxial structure, the elimination of the p-type implantation results in a decrease of device fabrication complexity and reduction of as-implanted lattice damage in the channel region. Meanwhile, a channel length of less than 0.5 μm can be obtained with the shielding of the BPL and the N implant region. The peak electric field of 1.03 MV/cm at the gate trench is reduced by 78.1% and 55.6% in comparison to the peak electric fields in the conventional UMOSFETs without and with bottom p well (BPW), respectively. Furthermore, the peak electric field is shifted from the corner of the gate oxide to the pn junction in the bulk region. In comparison to the conventional UMOSFETs with and without BPW, the breakdown voltage of 1602 V is increased by 48.3% and 86.3%, respectively, whereas the total switching loss of 18.84 mJ/cm2 is decreased by 28% and 74%, respectively. Baliga’s figure of merit is BFOM = 1100 MW/cm2, which is a very high value, showing the very high potential of the proposed UMOSFET structure for medium voltage power-electronic applications.