Abstract

In this study, the architecture of an interfacial switching memristor, which has a metal-insulatormetal structure of Pt/SrTiO<sub>3</sub>/Nb-SrTiO<sub>3</sub> was investigated. The performance of a neural network that uses memristors as its synapse components was also examined with system-level simulations. A finite element solver, COMSOL Multiphysics, was used to simulate synaptic device characteristics, specifically, the conductance change, using a series of pulses for a given architecture. An open-source software, NeuroSim, was used to simulate the ability of the neural network to recognize and identify handwritten digits. Electrostatics, mass transport, and thermionic emission equations were numerically solved in a fully coupled manner to model the Schottky barrier height modulation at the Pt/SrTiO<sub>3</sub> contact using the applied bias. The barrier height is a function of the oxygen vacancy concentration in the SrTiO<sub>3</sub> near the contact. The gradual change of the oxygen vacancy concentration profile caused by successive pulses results in the gradual change of conductance. Utilizing the simulations, the influences of device structure modification, and more specifically, changing the size of the Schottky contact, on long-term potentiation and depression were analyzed for planar devices. The results show that a smaller Schottky contact yields a higher digit recognition rate. Based on this finding, a three-dimensional device architecture that is vertically stackable was designed.

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