Simulation Study of a Junctionless Double Gate Tunnel Field Effect Transistor in 20nm Channel Length

Abstract

In this paper, a Junctionless Double Gate Tunnel FET (JL- DGTFET) has been designed and the performance is analyzed using Sentaurus 2D simulation technique. In JLT, uniform and heavy doping concentration is taken all over the source, channel and drain regions. Like TFET, tunneling in junctionless tunnel field effect transistor (JLTFET) also occurs due to BTBT mechanism. This paper comprehensively presents the novel architecture of the JL-DGFET which shows much promise in resolving the certain important issues related to the limitations of the conventional MOSFET and CMOS industry. From dc analysis of JL-DGTFET, high ON-current about ~10-3Amp and very low OFF-current about ~10-6 Amp are obtained which signify very low leakage currents and high ON-to-OFF current ratio. JLFET is usually popular due to lesser number of fabrication steps and less production cost comparing to other contemporary logic devices. Here device is simulated with the variation of different gate dielectric constant, gate and drain biases.