Simulation of hole phonon-velocity in strained Si/SiGe metal-oxide-semiconductor transistor

Abstract

Hole phonon velocity in a strained Si inversion layer grown on a relaxed SiGe substrate has been theoretically investigated. We used: (i) a 20 band k.p Hamiltonian method for the valence-band structure calculation, (ii) a self-consistent Schrödinger and Poisson equations solver for the confined hole subband determination, (iii) a direct matrix Boltzmann transport equation solver including hole-phonon interactions for the carrier velocity estimation in the subband structure. The present work particularly focuses on the influence of SiGe alloy composition and strained Si layer thickness on the hole dynamic in the inversion layer. Our results highlight the linear slope of the hole velocity enhancement factor with strain in the Si layer. But at the same time, large strain facilitates transfer in the parasitic channel at the Si/SiGe interface for which the carrier mobility is highly degraded. Consequently, in order to optimize a p-channel transistor with Si layer strain on SiGe virtual substrate, a compromise must be found between mobility in Si layer and parasitic transfer phenomenon in this interface. Our results suggest that a 10 nm Si layer thickness strain on a relaxed Si0.7Ge0.3 allows one to take advantage of the strain-induced enhancements of carrier transport characteristics. At the same time this compromise is realistic from a technological point of view.