Simulation of crosstalk in high-speed multilayer off-chip interconnections

Abstract

Listen

Translate article

Results of simulation of the electrical performance at 1 Gbit/s of a number of different off-chip interconnection architectures are presented, with emphasis given to the dependence of crosstalk on the geometries and dielectric constants of the insulating layers, as well as on the widths and separations of the conductors. The results indicate that crosstalk may be reduced not only by using low ϵ r values for the dielectrics, but also by reducing the conductor-to-wire ground separation which simultaneously neutralizes the role of the ϵ r value on crosstalk and line impedance.