Simulation of continuously logical ADC (CL ADC) of photocurrents as a basic cell of image processor and multichannel optical sensor systems

Abstract

The paper considers results of design and modeling of continuously logical analog-to-digital converters (ADC) based on current mirrors for image processor and multichannel optical sensor systems with parallel inputs-outputs. For such multichannel serial-parallel analog-to-digital converters (SP ADC) it is needed base photoelectron cells, which are considered in paper. Its have a number of advantages: high speed and reliability, simplicity, small power consumption, high integration level for linear and matrix structures. We show design of the continuously logical ADC of photocurrents and its base digit cells (ABC) and its simulations. We consider CL ADC for Gray and binary codes. Each channel of the structure consists of several base digit cells (ABC) on 20-30 CMOS FETs and one photodiode. The supply voltage of the ABC is 1-3.3V, the range of an input photocurrent is 0.1 – 10μA, the transformation time is 30ns at 5-8 bit binary or Gray codes, power consumption is about 1mW. One channel of ADC with iteration is based on one ABC-3(G) and SHD, and it has only 40 CMOS transistors. The general power consumption of the ADC, in this case, is only 50-100μW, if the maximum input current is 1μA. The CL ADC opens new prospects for realization of linear and matrix image processor and photo-electronic structures with picture operands, which are necessary for neural networks, digital optoelectronic processors, neural-fuzzy controllers, and so forth.