Abstract
The paper considers results of design and simulation of analogue-digital converters (ADC) based on current mirrors for the multi-sensor systems with parallel inputs-outputs. Such ADCs are named us as multichannel serial-parallel analog-to-digital converters based on current mirrors (M SP ADC CM). Compared with usual converters, for example reading, a bit-by-bit equilibration, and so forth, the proposed converters have a number of advantages: high speed and reliability, simplicity, small power consumption, the big degree of integration in linear and matrix structures. We discuss aspects of the design of M SP ADC CM in Gray and binary codes. It is offered, investigated and simulated the 6, 8 and more digit M SP ADC CM in Gray code and binary codes. Each channel of the overall structure consists of several base digit cells (ABC), with options for low power consumption with only one such ABC and analog memory (less than 20 CMOS transistors). Base digit cells (АВС) of such M SP ADC CM, series-pipelined in structures, consist of 20-30 CMOS transistors, one photodiode, have low (1-3.3) V supply voltage, work in current modes with the maximum values of currents (10-40) μA. Therefore such new principles of realization of high-speed low-digital M SP ADC CM have allowing, as shown by simulation experiments, to reach time of transformation less than 20-30ns at 5-8 bits of binary code and Gray code and the power consumption 1-5mW. The quantity of easily cascadable АВС depends on multi-bit ADC, and makes n, and provides quantity of quantization levels equal N=2 n . Such simple structure of M SP ADC CM with low power consumption ≤3÷5mWand supply voltage (3-7)V, and at the same time with good dynamic characteristics (frequency of digitization even for 1.5μm CMOS-technologies is 40 MHz, and can be increased up to 10 times) and accuracy (Δ quantization =156,25nA for I max =10μA ) characteristics are show. The range of optical signals, taking into account sensitivity of modern photo-detectors, can be 20-200 μW. Each channel of ADC, to reach the general power 50-100 μ W for low power consumption, can consist of only one such ABC and analog memory. To implement such serial ADC no more than 40 CMOS transistors are needed. The M SP ADC CM opens new prospects for realization linear and matrix (with picture operands) micro photo-electronic structures which are necessary for neural networks, digital optoelectronic processors, neural-fuzzy controllers, and so forth.
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