Simulation libraries for system-level design

Abstract

Raising the level of design abstraction to achieve a system synthesis capability requires electronic design automation (EDA) tools for design capture, analysis and verification at the new level of abstraction, as well as tools for synthesis at the next lower level of abstraction. It is essential that simulation libraries exist that support the new toolset. In system synthesis, elements of the desired product functionality will be specified as combinations of functional primitives in a high-order language or as flowgraph representations. Implementation trade offs will require the designer to simulate the performance of these functions when implemented in ASICs, FPGAs, or software. Simulation will require extensive libraries of primitives and their performance characteristics on a wide variety of hardware and software implementations. The paper considers system synthesis and some problems in system-level simulation. >