Simulation based performance comparison of transistors designed using standard photolithographic and coarse printing design specifications

Abstract

In this work a simulation based comparative study of organic field effect transistors designed using standard lithographic and printing designs is presented. The device simulations were performed using two-dimensional drift-diffusion equations with a Poole–Frenkel field dependent mobility model. Both photolithographic and coarse printing transistor designs employed common materials such as 150nm thick pentacene, 150nm thick parylene gate insulator, gold source-drain electrodes and aluminum gate electrodes. The major differences between the two fabrication specifications are the minimum source/drain line width and the transistor channel length. The typical specifications for the minimum line width and channel length were 2μm and 5μm for photolithography and 25μm and 20μm for coarse printing techniques, respectively. The gate, source, and drain capacitances and channel on-resistances at various channel lengths and gate overlaps have been extracted and presented specifically for both process schemes. Due to increased channel length and gate-source/drain overlap of printed electrodes relative to lithographic design, the resulting on-resistance and capacitances for coarse printing are significantly higher. These results demonstrate a substantial operating frequency reduction for printing design relative to photolithographic design. For the tested materials and designs it is shown that the cut-off frequency for the photolithographic process was 400kHz but decreased to a much lower 26kHz for the coarse printing process. Since printing technology uses various other materials, which typically have less performance than the ones used for this simulation, the actual printed device might have even lower performance than predicted here.