Abstract
The ultra thin body double gate FE layer TFET (UTB-DG-FE-TFET) is proposed and investigated in this work. Electrical performance parameters such as surface potential ψ (x), electrical field, drain current, sub-threshold swing, threshold voltage, and Ion/Ioff ratio are further analyzed using simulation-based analysis. Integration of Si: HFO2 ferroelectric layer on top and bottom surfaces make the structure that provides negative capacitance, higher on current, enormous surface potential, peak electric field, and improvement in SS with degradation in off Current. The suggested design is evaluated in comparison with FE-TFET and standard TFET structures. Finally, the impact of device geometry variants like ferroelectric layer thickness (tfe), intrinsic channel thickness tsi, interfacial layer types, interfacial layer thickness (tox) and channel length Lc on transfer characteristics are investigated through 2D TCAD Sentaurus Simulator for a clear validation of its optimization. The recommended work demonstrates that it is a suitable device enabling superior performance and helpful in ultra-low-power applications.
Highlights
Short channel effects (SCEs) and an increase in leakage current are the main issues with downscaling the CMOS technology node [1,2,3,4]
There is a need for in-depth research on steep subthreshold swing devices (< 60 mV/decade) like Tunnel field-effect transistors(TFETs) [10, 11], Impact ionization MOSFETs (I-MOS-FETs) [12], Nanoelectromechanical FETs (NEMFETs) [13] and Negative capacitance FETs [14]
The results indicate that the current level is raised by increasing the gate voltage, with a drop in the off-current compared to other TFETs
Summary
Short channel effects (SCEs) and an increase in leakage current are the main issues with downscaling the CMOS technology node [1,2,3,4]. There is a need for in-depth research on steep subthreshold swing devices (< 60 mV/decade) like Tunnel field-effect transistors(TFETs) [10, 11], Impact ionization MOSFETs (I-MOS-FETs) [12], Nanoelectromechanical FETs (NEMFETs) [13] and Negative capacitance FETs [14]. These Emerging devices have been seriously explored in recent years due to impending physical constraints of conventional CMOS devices.
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