Simulation and test of faults in WSI interconnect systems

Abstract

Different fault mechanisms in interconnect systems are considered, and their fault behavior is discussed. To diagnose these faults by a digital test, special features of test pattern choice and design modifications are proposed. In contrast with existing tests for VLSI circuits, the specific dynamic behavior of large line systems in wafer-scale integration (WSI) must be taken into account. Analog simulations for opens, shorts, and delay faults were necessary. A special simulator called LISIM was used, since existing tools have proved to be of little value for simulating lossy line systems. From these results a fault diagnosis by a digital test turns out to be problematic, since a safe diagnosis of the considered faults is not guaranteed. In some cases this problem can be avoided by applying special test patterns. Additionally, design modifications are proposed, so that all these types of faults can be detected. The modifications do not affect the signal-to-noise ratio more than usual designs, and do not lend to an additional delay. >