Simulation and Synthesis of Combinational Shifter using Reversible Gates

Abstract

In today’s world, the complexity of the chip is increasing as more and more devices are being connected on a single chip. As the number of devices on the chip increases, the devices must be scaled so that they can be accommodated on a chip of small size. Due to the high density of the chip, the power dissipation increases demanding better power optimization methods. One of the methods to achieve power optimization is by using Reversible logic. It can be used in Low Power CMOS designs, Quantum Computing, Nanotechnology and Optical Computing. The objective of this work is to design a Combinational Logic Shifterthat is most often found in digital systems, where they are used to move data bits to new locations on a data bus or to perform simple multiplication and division operations. The performance characteristics of the two proposed designsare verified using number of reversible gates, Garbage outputs and Quantum Cost. The performanceCharacteristics analysis is carried out in cadence digital design environment and CMOS implementation in cadence virtuoso.