Simulation and investigations on semiconductor materials and devices with surround gate geometry for high performance and low power nano scale applications

Abstract

All The device with surround gate geometry provides a better way to scale down the dimensions and optimization of power and performance for nano scale applications. The superior gate control can be obtained by novel materials and innovative techniques for various regions of the nano scale device. The surround gate (SG) field effect transistor provides high gain, high trans-conductance, reduced short channel effects and conditions for scaling the technology to sub nano scale. The device has been modeled using SILCAVO Atlas3d and DevEdit3D module also used for creating the device structure with integration of multiple layers of different materials. In this paper surround gate device input (ID-VGS) and output (ID-VDS) characteristics have been intensively studied and parameters including ION/IOFF ratio, DIBL, sub threshold slope extracted and compared with the conventional devices. The silicon nanowire field effect transistor (SiNWFET) with surround gate geometry at 0.6 V applied between source and drain exhibits threshold voltage (VTH) 0.204 V, drain induced barrier lowering (DIBL) 172 mV/V, sub-threshold swing (SS) 104.23 mV/dec, ION=440.1μA, IOFF=1.04 μA and ION/IOFF ratio 4.24e+02. The results demonstrate improvement in device parameters for the SiNWFET device as compared to other conventional MOSFETs. The result obtained for SiNWFET are also compared with FinFET and CNTFET devices. This research also investigates the integration of alternate channel, dielectric and gate materials into novel GAA device structure.