Simulation and analysis of through silicon via (TSV) based inductance structures

Abstract

The multichip packaging techniques have evolved over the years and have resulted in many solutions towards 3D integrated circuits. The key component to these technologies is Through Silicon Via. Typical TSV structures (2.5 micron diameter and 20 micron length and 5 micron diameter and 50 micron length) are analyzed using HFSS, with a view to generate data and understanding of TSV performance, specific to realization of integrated passives. TSV based inductor structure has been studied for different dimensions, number of turns and ground shielding. This has been compared with those of 2D spiral structures also analyzed using HFSS. Further, Via based vertical inductor realized within the metal layers of a sub micron technology has been simulated and analyzed for range of values and parasitics. The parasitics of TSV based inductance are found to be comparable with those of conventional spiral structure; this is specific to resistance of L which is of the same order in both cases, for a given inductance value. However, the area occupied on the die by a vertical TSV based inductor is considerably less than that by a conventional spiral inductor. The range of values that can be achieved by a TSV based L depends on the TSV length, which in turn depends on the interposer thickness in chip / wafer stacking. A 20 micron TSV based inductor has L in the range of 50–500 pH; a 50 micron interposer technology can generate much higher values of inductors. With considerable advantage on the die size, the TSV based inductor is a potential integrated passive for stacked 3D microcircuits.