Abstract
Abstract: There are various basic gates like NAND, NOR gates which are extensively used in the designing of the more complex circuits with use higher number of transistors such as MUXs, ADCs and any other circuits. In this paper, we have carried out the modelling of NOR gate at 130 nm technology, yet maintaining comparable performance than conventional CMOS NOR gate logic structure. The modelling includes schematics design and PCB layout design run of the above gates. Also, the simulation results of the gates are obtained at the same node with start time, step time, stop time, rise time, fall time and delay and power dissipation. In this all process have been carried out of a CMOS based NOR Logic Gate using Open-Source Software eSim. Keywords: Simulation, PCB, NOR, CMOS, eSim
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