Abstract

Chip sizes for submicrometre technologies are increasingly limited by protection circuitry, wire bonding and testing constraints. In the Letter, protection circuitry is examined as a chip wide network and optimised to give enhanced performance for latch-up and ESD without adding to the chip size.

Full Text
Paper version not known

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.