Abstract

True random number generators (TRNGs) are needed in cryptography for key generation, in challenge response authentication procedures and for countermeasures against power analysis attacks. Such true randomness requires to utilise random physical hardware effects. It is the goal to make the TRNG usable for different semi-conductor technologies (including field programmable gate arrays (FPGAs)). This approach is based on ring oscillators with multiple taps in combination with a simple post processing by exclusive OR antivalence (XOR) compression. Verifications with a test chip and several FPGA implementations showed that standard digital library elements and the digital design flow can be used without any constraints for compilation and special layout rules. A proper choice of sampling frequency and compression coefficient ensures a random output with extremely low bias for different technologies which can be checked on-line easily. It was shown that for passing the on-line test with a given bias limit the generated random data passes the statistical tests.

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