Simple and Accurate Method of Modeling Gate Current of N-Channel Metal–Oxide–Semiconductor Field-Effect Transistor

Abstract

A mathematical method of modeling the gate leakage current IG is presented in this work. Both the shallow trench isolation and source drain extension effects on IG are included. With suitably chosen transistor dimensions, parameter extraction can be performed using the devices' drawn size, and the troublesome effective device length and width are not necessary in this model. The extracted parameters were used to predict the IG of devices with other different dimensions. Transistors fabricated with 90 nm technologies were examined.