Abstract
A mathematical method of modeling the gate leakage current IG is presented in this work. Both the shallow trench isolation effect and the source drain extension effect on IG are included. With suitably chosen transistor dimensions the parameter extraction can be performed with the devices' drawn size, the effective device length and width is not necessary in this model. The extracted parameters were used to predict IG of devices with other dimensions. The error between calculated results and measured results is about 3%
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