Silicon-on-insulator substrates with buried tungsten silicide layer

Abstract

Tungsten silicide layers can be incorporated into silicon-on-insulator (SOI) substrates produced by direct wafer bonding. The series resistance of collectors/drains in bipolar or smart-power circuits can be reduced to 2 Ω/sq. The out-diffusion of the buried implanted collector contact during the post-bond anneal can be eliminated by using rapid diffusivity of donors and acceptors in tungsten silicide subsequent to bond anneal. Optimisation of this process can provide better matching of vertical complementary bipolar transistors. A novel silicon-on-silicide-on-insulator structure is proposed for integrating p–i–n diodes with low loss coplanar wave-guide lines. This incorporates a polysilicon surface layer on the high resistivity handle wafer and a tungsten silicide back contact to the diode. CPW lines with microwave losses of 2 dB/cm have been obtained at 30 GHz. The incorporation of a tungsten silicide layer below the buried silicon dioxide layer can be used as a ground plane. A tungsten silicide ground plane used with a standard SOI test structures was found to increase the suppression of cross-talk by 20 dB in the frequency range 1–10 GHz. Other potential applications such as ground plane and double-gate MOSFETs are discussed.