Silicon-Based Nanowire MOSFETs: From Process and Device Physics to Simulation and Modeling

Abstract

Over the past few years tremendous progress has been made on the process, application, device physics and compact modeling of nanowire MOSFETs. We would like to review the above aspects of silicon-based nanowire, focusing on its crucial compact models and the circuit performance demonstration based on our group research work and understanding on nanowire MOSFET progress. Nanowire MOSFETs are recognized as one of the most promising candidates to extend Moore’s law into nanoelectronics era. Both the top-down (Singh et al., 2008) and bottom-up (Lu & Lieber, 2006) approaches are widely studied to prepare ultra small nanowire. With bottom-up method, nanowires are generally synthesized by using metal nanoclusters as catalysts via a vapor-liquid-solid process (Lu & Lieber, 2006). After growth nanowires are transferred to silicon substrate to form FET structure. With top-down technique there are various fabrication approaches, such as hard mask trimming, etching in H2 ambient and stress limited oxidation (Singh et al., 2008). 5-nm gate length device has been demonstrated (Liow et al., 2008). Nanowire MOSFETs prepared with both methods find application in logic circuits (Singh et al., 2008), memory (Singh et al., 2008) and sensors (Stern et al., 2008). Due to the quantum confinement in cross section of nanowire MOSFETs, especially of nanowires with diameter smaller than 15nm, electron mobility behaves differently from its bulk counterpart. Phonon-limited electron mobility decreases with reducing the wire size (Kotlyar et al., 2004) while total electron mobility is enhanced due to volume inversion at high transverse field (Jin et al., 2007). Although whether or not ballistic transport can occur in the silicon nanowire MOSFETs with ultrasmall channel length is disputable (Ferry et al., 2008), it deserves our attention. In the ballistic transport regime, carrier scattering in the device channel is totally suppressed. The study of ballistic transport in nanowire MOSFETs provides the upper limit to their performances. Under extreme scaling of nanowire MOSFETs, the atoms in nanowire cross section are countable. It is believed that the change in bandstructure of one dimensional nanowire influences the device performances (Neophytou et al., 2008). The above mentioned phenomenon are studied and simulated with various numerical approaches and also need to be accounted for in the advanced compact models.