Abstract

A scheme is presented for the estimation of signal delay in RC networks with floating capacitors. The scheme involves finding signal delays in the network with the floating capacitors either replaced by open circuits or short circuits. Preliminary experiments have shown that the scheme is viable and could be used to build an efficient RC simulator that handles RC networks with floating capacitors. The results are pertinent to the use of linear lumped RC networks in timing simulators to model MOS digital circuits.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

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