Signal and Power Integrity Analysis of High-Speed Links with Silicon Interposer

Abstract

Silicon interposers are frequently used in memory and network processor systems to closely integrate multiple chips and improve the performance of high-speed systems. The proximity provided by silicon interposer greatly improves bandwidth, power, and latency by simplifying communication and clocking of the links. However, the design of silicon interposer systems poses new challenges in managing the signal and power integrity of the systems. In signal integrity, the design of spiral inductors which are critical in high-speed links requires special consideration to minimize the interaction between the on chip spiral inductance and the low resistivity silicon interposer. In power integrity, the impact of on-interposer decoupling capacitors to suppress the mid-frequency noise depends on the design rules of the top layer of the silicon interposer. The resistive and capacitive characteristics of silicon interposer can determine the effectiveness of the decoupling capacitors placed on the interposer. Thus, careful analysis of on-die inductor and interposer decoupling capacitors is required.