Sidewall gated double well quasi-one-dimensional resonant tunneling transistors

Abstract

We present gating characteristics of submicron vertical resonant tunneling transistors in double quantum well heterostructures. Current–voltage characteristics at room temperature and 77 K for devices with minimum feature widths of 0.9 and 0.7 μm are presented and discussed. The evolution of the I–V characteristics with increasing negative gate biases is related to the change in the lateral confinement, with a transition from a large area 2D to a quasi-1D. Even gating of multiple wells and lateral confinement effects observable at 77 K make these devices ideally suited for applications in multi-valued logic systems and low-dimensional structures.