Side-channel leakage assessment metrics and methodologies at design cycle: A case study for a cryptosystem

Abstract

Current EDA (electronic design automation) tools are not capable to consider side-channel vulnerabilities at design time. Therefore, designers should manage such security considerations in their designs manually. One of the main reasons for this glaring shortcoming is the lack of feasible metrics to assess the immunity of various crypto-system designs against various attacks at design time. In this paper, we suggest and categorize the required features for a reliable metric for side-channel security assessment in EDA tools and then we show that T-test can be used as a reliable metric to assess the impact of such attacks in a crypto-system. We also present a toolchain called Time-based Power Simulation engine (TPS) to perform required gate-level power measurements during the design phase. TPS is used for tests that are conducting in this research. Using this toolchain, we evaluate the T-test as an assessment metric for analyzing the security at design time against side-channel attacks. Results of our analysis show that it can be used efficiently as a feasible metric to measure the vulnerability level of a design against the SCA attacks. Moreover, the results of the T-test at the design phase show that using different bits of intermediate round values as selection functions in our DES cipher implementation leads to very different levels of information leakage.