Si/Si 1−xGe x heterostructure field effect transistors fabricated using a low thermal budget CMOS process

Abstract

Strained Si/Si 0.75Ge 0.25 heterostructure field effect transistors (HFETs) have been fabricated using a modified, low-thermal budget CMOS process with deposited gate oxides. Transmission electron microscopy demonstrates the integrity of the strained-Si quantum well after processing. The transconductances of the HFET devices are higher than the similarly processed Si MOSFET devices. Electrical characterisation data is presented which suggest that thinner gate oxides, higher Ge contents in the virtual substrate and optimisation of the p-type substrate doping profile will improve device performance.