Shortest Partial Path First Algorithm for Reconfigurable Processor Array with Faults

Abstract

With the development of very large scale integration (VLSI) technologies, a large numbers of the processing elements (PEs) can be integrated on a single chip. The increasing density of VLSI arrays leads to the increase of the probability of PEs malfunction during normal operation of the system. Faulttolerant techniques become a meaningful research topic to obtain fault-free logical array, in order to guarantee the system stability and reliability. In this paper, we propose a fast algorithm to reconfigure logical arrays based on the strategy of shortest partial path first extension. The algorithm selects the partial path with the minimum number of long interconnect to extend, as the partial path is often the part of the optimal logical column that is to be constructed. Thus, the proposed algorithm can rapidly generate the optimal logical column, as it is able to avoid the search for all possible paths related to the fault-free PEs, without loss of harvest. Experimental results show that the state-of-theart can be improved up to by 38.9% in 128 × 128 host array with 20% faults, in terms of running time.