Abstract
Bottom-up self-assembled planar nanowires (NWs) are of great interest for device application because they can be readily integrated using conventional processing technique. Planar GaAs NWs have been demonstrated to have great crystal quality (free from top-down dry etching damages) and high electron mobility. Considering NWs' 3D geometry, planar NW-FETs inherently benefit from the enhanced electron confinement and electrostatic gate control which are essential to suppress short channel effects and enable the down-scaling of modern transistors. We had fabricated multiple channel planar NW high electron mobility transistors (NW-HEMTs) with self-aligned intrinsic planar <110> GaAs NWs capped with Si doped Al <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</inf> Ga <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1−x</inf> As thin film as the channel on semi-insulating (100) GaAs substrates and demonstrated the feasibility of wafer-scale electrical uniformity of bottom-up NW-FETs previously [1–4]. However, these prototype multiple channel planar NW-HEMTs were of 1.2µm gate length and ∼250nm NW diameter in the channel.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
