Short critical area model and extraction algorithm based on defect characteristics in integrated circuits

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In the process of nano-electronic circuit design, there are defects inevitably. Due to the variety of defects and nets on circuits, the extraction of the critical area leading to the short circuit fault has become the bottleneck of layout optimization and of integrated circuit yield estimation. This paper proposes a new model of short critical area and extraction algorithm based on short circuit faults caused by redundant defects, combining the redundant defect features and mathematical morphology theory. Firstly, defect feature sizes and the nets ranges of the circuit are extracted. Secondly, according to the definition of short critical area and utilizing the expansion operation of mathematical morphology a new model of short critical area of regular nets is derived. Finally, extraction algorithm of short critical area is designed and implemented in accordance with the new model. The new model and extraction algorithm have the characteristics of being more generic and being independent of the shape features of defects and nets. Compared with the existing models, the new model has the similar performance however the extraction algorithm has significantly raised time efficiency. Furthermore, the extraction algorithm is more efficient than the previous algorithm which is based on mathematical morphology and non-model method. The experimental results on the real layouts of synthesized OpenSparc circuit and MUSB L70 show that the proposed method is accurate and effective.