Shallow trench isolation geometric influence of a recessed surface on array-type arrangements of nano-scaled devices strained by contact etch stop liner and Ge-based stressors

Abstract

Given the reduction in size of hole-containing metal-oxide-semiconductor field-effect transistors (pMOSFETs) to break Moore's law, extensive researches have been conducted to improve the performance of nano-scaled devices with the use of strained engineering. The layout patterns of devices combined with the introductions of manufacturing processes would cause recessed surfaces of shallow trench isolation (STI) and change the stress-induced mobility of the whole transistors. To address this issue, a process-oriented stress simulation with a 20nm nano-scaled short channel device and a 100nm gate width is presented to extract channel stress components and calculate mobility gain, subsequently. Moreover, the layout effect of dummy active of diffusion is also considered. The proposed pMOSFET is composed of STI, a source/drain lattice mismatched silicon-germanium alloy, and a compressed contact etch stop liner (CESL) stressor. The recessed height of STI is reduced from 0nm to 15nm in the planarization process. The results show the recessed height effects of STI on the stresses and mobility variation of device channel is not obvious. By contrast, CESL with intrinsic stress plays an important role to modulate device mobility.