Abstract
CMOS technology scaling dictates the reduction of the Source/Drain (S/D) junction depths to reduce punch-through and short channel effects. But simultaneously, lower contact resistances are needed as the device channel resistance decreases low S/D junction sheet resistance is required for improved density, and low S/D junction leakage should be maintained for reduced stand-by power and longer refresh time. In this paper, these conflicting requirements and several key technology elements for shallow junctions including silicide with thin TiSi 2 and the application of rapid thermal processing (RTP) will be presented. 0.25 μm CMOS S/D with junctions depths in the range of 0.1μm-0.15μm and less than 10 Ω□sheet resistance, exhibiting low leakage and contact resistance are demonstrated.
Published Version
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