Shallow Extension Engineered Dual Material Surrounding Gate (SEE-DM-SG) MOSFET for improved gate leakages, analysis of circuit and noise performance

Abstract

The leakages in off state, particularly Gate Induced Drain Leakage (GIDL) has been addressed and reduced by proposing a Shallow Extension Engineered Dual Material Surrounding Gate (SEE-DM-SG) MOSFET. The shallow extensions create an insulating layer, which acts as a diffusion stopper and thereby suppresses the off state leakages. It is done by comparing the off-state performance of SEE-DM-SG MOSFET with Dual Metal Surrounding Gate (DM-SG) MOSFET and Surrounding Gate (SG) MOSFET. GIDL current is being reduced to an order of 10−12 A. Drain Induced Barrier Lowering (DIBL) has been curtailed to a greater extent in SEE-DM-SG MOSFET when compared with DM-SG MOSFET and SG MOSFET. GIDL has been extensively investigated for different drain voltages and temperatures; in order to study their impact on it. It was so found that GIDL was minimal for SEE-DM-SG MOSFET under different bias and temperature conditions. Arrhenius plot has also been plotted and deeply investigated as it instigates the GIDL activation energy (EA). It has been so found that SEE-DM-SG MOSFET poses higher EA and thereby suggests minimal BTBT (Band To Band Tunneling). So as to enhance the device applicability for low noise amplifier, the noise performance of SEE-DM-SG MOSFET has also been deeply investigated. Noise conductance (NC) and Noise Figure (NF) have been significantly curtailed in SEE-DM-SG MOSFET over DM-SG and SG MOSFET. A CMOS inverter has also been designed using SEE-DM-SG MOSFET and the output characteristics have also been compared for the aforesaid device architectures and higher Noise Margin has been observed in SEE-DM-SG MOSFET, making it more immune to noise.