Abstract
In the fabrication of CMOS devices with sub-3 nm gate oxides, we have observed severe variation of the oxide thickness (t/sub ox/). For devices with 2.5 nm t/sub ox/ at the center of the channel, the physical t/sub ox/ ranges from 1.8 nm to 4.2 nm at various channel positions. This is caused by different oxide growth rates determined by the orientation and stress conditions of the local Si surface, especially at the rounded corners of the shallow-trench isolation (STI). In addition, poly-Si intrusion from the gate electrode also causes local t/sub ox/ thinning. Such severe variation of t/sub ox/ becomes the challenge of STI engineering, gate-oxide scaling and qualification.
Published Version
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