SERSim: a soft error rate simulator and a case study for a 32-bit OpenRisc 1200 microprocessor

Abstract

Soft error is becoming increasingly important in the era of sub-100 nanometer very large scale integrated (VLSI) circuits. This article focuses on the impact of soft error on an OpenRisc 1200 CPU core. A C++ programming language based soft error analysis tool, with the name of SERSim, is created to perform a detailed exploration of this impact. The estimation error of SERSim ranges from 0.1% to 4.5%. With the help of SERSim, we find out that almost all the glitch widths are narrower than 200 ps in a 45 nm OpenRisc 1200 microprocessor circuit. This result is important for soft error rate reduction of VLSI circuits. The outputs of the multiplier of the OpenRisc 1200 microprocessor are found to be the most troublesome. Those outputs, which represent only 3% of the circuit outputs, produce more than half of the circuit bit error rate. A significant impact of performance requirements on circuit vulnerability to soft error is observed in our experiment. The difference helps us to analyse the estimation error of high-level soft error models.