Abstract
This paper presents a low-noise front-end readout application specific integrated circuit (ASIC) for CZT detectors. A cascode amplifier based on split-let topology is selected to realize the charge-sensitive amplifier (CSA) to achieve low noise performances. A leakage-current-compensation circuit is added to suppress the leakage current of from 0 to 10 nA. The output of the CSA is connected to a slow shaper implemented by a CR-(RC) <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> semi-Gaussian architecture. In the time branch, the CSA output is followed by a fast shaper for the trigger acquisition. A digital monostable circuits is designed to adjust the delay of trigger signals so that the peak value of the shaped voltages can be tracked. The sampled voltages are stored into an analog memory. Based on the above topology, a 16-channel front-end readout prototype chip (named as SENSROC5) is designed and implemented in 0.35 μm CMOS process. In this chip, the radiation-hardness layout techniques are adopted. The die size is 2.12 mm×4.60 mm. The input range of the ASIC is from 2000 e-to 180000 e-, which is suitable for the detection of the X-and gamma ray from 11.2 keV to 1 MeV. The post-simulated results are listed in the following. The gain of the readout channel is 40.2 V/pC. The ENC is 90 e- at zero farad plus 15 e- per picofarad. The nonlinearity is less than 3 %. The crosstalk is less than 2 %. The power dissipation is about 16.5mWplus 3.1 mW/channel.
Published Version
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