Sensitization Input Vector Impact on Propagation Delay for Nanometer CMOS ICs: Analysis and Solutions

Abstract

We report and analyze the dependence of complex gates delay with the sensitization vector and its variation-that gets up to 40% in 65-nm CMOS technologies-and include its effect in the path delay estimation-that can be in the order of 16%. The gate delay is computed from a simple polynomial analytical description that requires a one-time library parameter extraction process, making it highly scalable. An STA tool based on a single-pass true path computation is used to determine the critical path list. Since it does not rely on a two-step process, it can be programmed to find efficiently the N true paths from a circuit. Results from various benchmark circuits synthesized for three commercial technologies (130, 90, and 65 nm) provide better results in number of paths reported and delay estimation for these paths compared to a commercial tool. The impact of delay variation with the sensitization vector for paths with complex gates reveals as a significant mechanism that must be considered as it is comparable to the impact of parameter variations or interconnect-induced delay.