Abstract
It is widely believed that any true (or sensitizable) critical path of length /spl ges/2 T must be speeded up in order for a circuit to have a delay <T. I demonstrate that this notion is pessimistic. Many true paths can never affect the delay of the circuit-whenever such a path propagates a signal, some other path that is at least as long also propagates a signal. The theory for a new classification of paths based on the impact on the circuit delay is presented and conditions are given under which a path (or a set of paths) must be speeded up in order to improve the circuit delay. The conditions for the categorization are independent of the delays in the circuit and are valid for all delay assignments. This work indicates that the widely employed notions of true and false paths may be misleading both for timing optimization and delay analysis of logic circuits.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
