Sense-Node Capacitance Reduction for SOI Pixel Sensor With Small Detection p-Well

Abstract

A silicon-on-insulator pixel sensor with small detection p-well is researched and simulated to reduce the sense-node capacitance while maintaining a widespread collection area and uniform field within the sensing volume. In this pixel structure, two p-doped wells are adopted. A transfer gate is employed to form a transport channel for charge carriers from one p-doped well to another when transfer gate is ON, or to isolate the two p-doped wells when transfer gate is OFF. A fully depleted buried p-well is formed for charge collection and storage, which is not connected to the readout electrode. Some key parameters have been studied. Numerical simulation results show that the proposed device can work effectively, but charge transfer efficiency is low for a small amount of charge, which needs a further improvement.